Many conventional commercial products, including computer systems as well as other digitally controlled products, have integrated circuits (ICs) that must communicate with one another. One way of implementing this communication is through the use of a data bus via which digital information is transmitted. Such busses take different forms. One type of bus is a two-way, two-line connection between different ICs or modules referred to as the “I2C” bus. Although there are other busses as well, the I2C bus is exemplary for the purposes herein.
The I2C bus uses two active wires and a ground connection. The active wires are referred to as the “serial data line” (SDA) and the “serial clock line” (SCL). The signaling methods used with the I2C bus make use of unique addresses assigned to each of the devices connected to the bus. The bus protocol involves a “master/slave” arrangement in which a device that initiates a data transfer is recognized as the “master” while other devices are the “slaves.”
The most common form of I2C uses 7-bit addressing, allowing for a maximum of 128 unique device addresses. Device addresses appear on the bus with an eighth bit appended in the least significant position as a “1” or “0” to indicate whether a given transaction is a read or write, respectively. Thus, a given device may consume two bus-form addresses, given in hexadecimal as, for example, A0h (write) and A1h (read). The I2C addresses listed for devices in the remainder of this document will use this bus-form address notation, with <0>for the read/write bit.
Since the I2C bus protocol makes no provisions for automatic assignments of device addresses to slave devices, standard I2C devices must be hardware-configured such that each device knows its unique slave address unambiguously. On typical I2C integrated circuits, this address selection is performed via the hard-wiring of a set of device pins to logic HIGH or LOW, corresponding to some or all of the bits of the I2C 7-bit address. Thus, when an I2C transaction is issued on the bus, each slave device can discern, based upon address, the transactions in which it needs to participate as a slave, and which to ignore. Due to low-cost design goals applied to most standard I2C slave devices, the number of such address-select pins is typically limited to three. Thus, a manufacturer of an I2C slave device selects permanently the upper 4-bits of the device's I2C address, allowing the system designer to configure the lower 3-bits via the address-selection pins, limiting the number of unique selectable I2C addresses to eight. Thus, although the I2C address map affords 128 unique slave addresses, a system designer may typically be limited to a maximum of eight instances of a given device type. This limitation is referred to as “address exhaustion.”
Manufacturers of I2C slave devices typically assign different address ranges to devices that perform different functions. For example, I2C serial EEPROM devices typically have device addresses in the Axh range (A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh), where bits <3:1>are selected via address-selection pins as described above. Similarly, a general-purpose input-output device may have addresses in the 40–4Eh range. If a system designer requires more similar devices than the devices' address-selection pins can accommodate, then special mechanisms must be employed to ensure that all such devices are uniquely addressable.
The common solution in the prior art for the limited address space of the I2C bus is the use of an “I2C multiplexer.” An example of such a multiplexer is the “PCA9544 4-channel I2C Multiplexer and Interrupt controller” made by Philips Semiconductors, Sunnyvale, Calif. The use of the multiplexer divides the bus into a main segment and a number of subsegments. The multiplexer connects only one of the subsegments to the main segment at any point in time. An arrangement such as this is shown schematically in FIG. 1.
FIG. 1 shows an I2C system wherein an I2C multiplexer is used to overcome the address exhaustion problem described above. As shown in the figure, the two signal lines of the bus, SDA and SCL connect to a master device 10, slave devices 12, having hexidecimal addresses 42h and 44h, respectively, and an I2C multiplexer device 14. Four pairs of signal lines 16 extend from the multiplexer with each pair forming an I2C subsegment. Each subsegment 16 has connected to it eight slave devices, shown at addresses A0h, A2h, A4h, A6h, A8h, AAh, ACh, and AEh. The aforementioned multiplexer is a 1-of-4 bidirectional multiplexer, providing four subsegments. With this arrangment of slave devices attached to each subsegment, the multiplexer may be used to increase the number of similar slave devices.
The control of an I2C multiplexer such as that of FIG. 1 is accomplished by explicit I2C transactions performed on the main bus by the master device. Using this control mechanism, the master device communicates with control registers internal to the multiplexer itself, selecting one of the four subsegments to be electrically connected to the main bus. Once this bus selection is made, the set of slave devices visible to the master device includes those on the selected subsegment and those on the main bus. Since only one subsegment is seen by the master at a time, the subsegment slave devices on the different subsegments share slave addresses. Thus, the master device must properly coordinate the subsegment selection via the multiplexer device with the slave address issued on the bus to ensure that the proper slave device is accessed in a given transaction.
A problem with the use of multiplexers such as that shown in FIG. 1 is that an I2C master on the main bus is required to perform two separate bus operations to access a slave device; one to switch the multiplexer, and one to access the slave on the selected subsegment. However, the multiplexer approach is typically limited to use with one master device. This is because, if more than one independent master was to access the bus at the same time, one master could inadvertently switch the multiplexer after another master had selected its desired subsegment, but before the other master had completed its transaction to the desired slave device, leading to errors in operation.